Consider we have two levels of cache, backed by a main memory (RAM). You are given with the following information about the access time for different level in the memory hierarchy L1 cache costs 1 cycle to access and has a miss rate of 8% L2 cache costs additional 5 cycles to access and has a miss rate of 4% RAM costs additional 40 cycles to access (and has a miss rate of 0%) What is the average memory access time (AMAT)?

Consider we have two levels of cache, backed by a main memory (RAM). You are given with the following information about the access time for different level in the memory hierarchy L1 cache costs 1...

Consider we have two levels of cache, backed by a main memory (RAM). You are given with the following information about the access time for different level in the memory hierarchy

L1 cache costs 1 cycle to access and has a miss rate of 8%

L2 cache costs additional 5 cycles to access and has a miss rate of 4%

RAM costs additional 40 cycles to access (and has a miss rate of 0%)

What is the average memory access time (AMAT)?

Jun 05, 2022

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Consider we have two levels of cache, backed by a main memory (RAM). You are given with the following information about the access time for different level in the memory hierarchy L1 cache costs 1...

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