Consider two different implementations of the same instruction set architecture. The instructions can be divided into four classes according to their CPI (class A, B, C, and D). P1 with a clock rate...

Consider two different implementations of the same instruction set architecture.
The instructions can be divided into four classes according to their CPI (class
A, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIs of 2, 3, 4, and 4, and
P2 with a clock rate of 3 GHz and CPIs of 2, 2, 3, and 1. Given a program with
a dynamic instruction count of 1.0E6 instructions divided into classes as
follows: 10% class A, 20% class B, 50% class C, and 20% class D, which
implementation is faster?