Consider the unpipelined machine with 10 nano seconds clock cycles. It uses four cycles for ALU operations and branches whereas five cycles for memory operation. Assume that the relative frequencies...

Extracted text: Consider the unpipelined machine with 10 nano seconds clock cycles. It uses four cycles for ALU operations and branches whereas five cycles for memory operation. Assume that the relative frequencies of these operations 40%, 20% and 40% are respectively. Suppose that due to clock skew and setup, pipelining the machine adds 1 nano seconds overhead to the clock. How much speed up in the instruction execution rate will we gain from a pipeline?