Consider the following sequential circuit and answer the following requests. Q=7ns, Tset-up=3ns Th=1nsNAND and AND gates: TLH=THL=2nsLatch SR: delay from Sor R to Q or Qn is 4nsRequest 1:-...

Consider the following sequential circuit and answer the following requests.


Extracted text: Consider the sequential circuit shown in the figure and the delays reported below: D FF: Tck=>Q=7ns, Tset-up=3ns Th=1ns NAND and AND gates: TLH=THL=2ns Latch SR: delay from Sor R to Q or Qn is 4ns Request 1: - Assuming initial states Q1=0 and Q2=0, calculate the initial state of the output Out - Calculate the delay between the variation of the state in Out and the first rising edge of the CK - Calculate the delay between the variation of the state Q2 and the first rising edge of the CK Request 2: Calculate the maximum CK frequency Val D Q D Q Q2 S Q Rpu Qn Qn R Qn CK Out В