Consider the following execution in a processor with forwarding implemented, and with stall penalty of one clock cycle. Assume [SS1] is not zero. Clock CCO CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8...

Consider the following execution in a processor with forwarding implemented, and with stall penalty of one clock cycle. Assume [SS1] is not zero. Clock CCO CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9CC10cC11CC12CC13 IF ID EX MEM WB beq $S1, SZero, SOMEWHERE add $S3, $S2, SS1 sw SS3, 32 (SS2) The total number of stalls for the sequence is 1. 2 2. 3 3. 1 4. none of the above