Consider the common source amplifier in Fig. P4.12 driving a capacitive load of . Assume and the gate dc bias voltage is set to keep in saturation. What current and device width are required to...


Consider the common source amplifier in Fig. P4.12 driving a capacitive load of . Assume and the gate dc bias voltage is set to keep in saturation. What current and device width are required to maximize the small-signal dc gain while maintaining a 3-dB bandwidth of at least 10 MHz?


a. Use the NMOS device parameters for the 0.18- μm CMOS process in Table 1.5.


b. Use the NMOS device parameters for the 45-nm CMOS process in Table 1.5. Compare your results with SPICE.




Dec 21, 2021
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