Consider the clocked comparator shown in Fig XXXXXXXXXXin the 0.18- technology of Table 1.5 and assuming                               2 W L ----- ⎝ ⎠ ⎜ ⎟ ⎛ ⎞ n W L ----- ⎝ ⎠ ⎜ ⎟ ⎛ ⎞ p = = 2 VDD = 1.8...

Consider the clocked comparator shown in Fig. 17.25 in the 0.18- technology of Table 1.5 and assuming

                              2 W L ----- ⎝ ⎠ ⎜ ⎟ ⎛ ⎞ n W L ----- ⎝ ⎠ ⎜ ⎟ ⎛ ⎞ p = = 2 VDD = 1.8 V

If the MOSFETS in the inverter are ideal except for each having a output impedance when active, find the minimum differential input that will cause a 0.2-V change (use a linear analysis). Assuming this minimum differential input corresponds to , what is the maximum number of bits that this comparator could determine in a flash A/D converter?