Consider the capacitive-reset gain circuit during each of the two clock phases depicted in Fig XXXXXXXXXXWhat is the feedback factor, , in each of those two configurations? Which clock phase will,...

Consider the capacitive-reset gain circuit during each of the two clock phases depicted in Fig. 14.35. What is the feedback factor, , in each of those two configurations? Which clock phase will, therefore, result in the worstcase phase margin for the feedback circuit?