Consider the architecture as shown and the following instruction: link a6, #-8 Internal bus CONTROL IR PC 0 12 4 Y Addr bus (to MEM) Select MAR mux MDR ALU Data bus (to/from MEM) Regs (A0-AN) Give the...

Extracted text: Consider the architecture as shown and the following instruction: link a6, #-8 Internal bus CONTROL IR PC 0 12 4 Y Addr bus (to MEM) Select MAR mux MDR ALU Data bus (to/from MEM) Regs (A0-AN) Give the steps and control signals for implementing this instruction using the table on the next page. Include the instruction fetch. Efficiency will be part of your mark on this question. Comments are optional, but may increase part marks-register transfer notation can be a helpful comment in this case. Use ONLY the following control signals: IRin, PCin, PCout, Zin, Zout, Yin, MDRIN, MDRout, ALUadd, ALUsub (subtract: bus value minus selected value), select Y, select 0, select 1, select 2, select 4, READ, WRITE, WMFC, END