Consider a pipelined system with four stages: IF, ID, EX, WB. Following chart shows the clock cycles required by instruction to complete each stage. Writ tructions Fetch(IF)Decode(ID) Execute(EX)...

CO

Extracted text: Consider a pipelined system with four stages: IF, ID, EX, WB. Following chart shows the clock cycles required by instruction to complete each stage. Writ tructions Fetch(IF)Decode(ID) Execute(EX) back(\ 10 1 1 2 11 2 2 1 12 2 2 13 1 1 1 14 3 1 2 How many clock cycles are required to complete the instructions? NNN