Consider a cache memory with blocks of 23 words (1 word = 4 bytes) , with a bus Main Memory - Cache of (23x 32) bits , and with 1 clock cycle to send the address, a row cycle time (DRAM) of 13 cycles...

Consider a cache memory with blocks of 23 words (1 word = 4 bytes) , with a bus Main Memory - Cache of (23x 32) bits , and with 1 clock cycle to send the address, a row cycle time (DRAM) of 13 cycles (one column only) and 1 clock cycle to return a word. Calculate the bandwidth of the system in byte per clock cycles (bandwidth = number of bytes per clock cycles) for the transfer of one block from Main Memory to Cache Memory for an interleaved main memory system with 23 banks (width of any bank: one word). Provide the solution with at least 2 decimals.