Please design a MIPS processor that supports only the addi and the AAA rs, rt, imm instructions. The AAA rs, rt, imm is an I-type instruction that does the following: · PC will be rs - imm · If rs ==...

Computer organization problem on MIPS processor design.


Please design a MIPS processor that supports only the addi and the AAA rs, rt, imm instructions. The AAA rs, rt, imm is an I-type instruction that does the following: · PC will be rs - imm · If rs == imm, rt will be PC+4; otherwise, rt will not be changed (a) (9 points) Please design the datapath, add 2-1 MUX when necessary. Please show clearly the indices of the bits near the wires. Please give clear indices to the 2-1 MUXes starting from 1. (b) (3 points) Please determine the values of the control signals, including the selection signal of the 2-1 MUXes, as well as RegWrite, by filling in the table. In case of “don’t care”, please write down “X.” Assume other control signals have been generated correctly. (c) (3 points) Assume the opcode of addi is 000000, and the opcode of AAA is 100000. Please write down the logic functions of the control signals. Please use ins31 to refer to bit 31 of the instruction, and Z to refer to the zero output of the ALU. In case of “don’t care,” assume the control signal should be 0. addi AAA (rs != imm) AAA (rs == imm) RegWrite MuxCtrl1 MuxCtrl2 RegWrite = MuxCtrl1 = MuxCtrl2 =