Use the values on the table and not other values pls. Thank you
![column width=15<br>Appendix A<br>Fetch and decode<br>column width=26<br>column=10 column width=15<br>column width=26<br>Instruction<br>Boolean condition<br>RTL<br>name<br>Fetch<br>TO)L:<br>AR<--PC, SC<-- 0<br>TI)L:<br>IR<-- M[AR].PC<--PC+1<br>(DO:D7) <--IR(12:14), I<-- IR(15),<br>row<br>Decode<br>T2)L:<br>AR<-- IR(0:11)<br>hight-30<br>Indirect<br>D7'.LT3)L:<br>AR<--M[AR]<br>Input/output instructions<br>Instruction Hexadecimal Boolean condition<br>RTL<br>INP<br>F800<br>(D7.I.T3.IR(11))L:<br>AC(0:7) <-. INPR,<br>OUT<br>F400<br>(D7.I.T3.IR(10))L:<br>OUT <-- AC(0:7), SC <-- 0<br>SKI<br>F200<br>(D7.I.T3.IR(9))L:<br>(FGI)L:PC <-- PC+1,SC <-- 0<br>SKO<br>F100<br>(D7.1.T3.IR(8))L:<br>(FGO)L:PC <- PC+1,SC <-- 0<br>ION<br>FO80<br>(D7.1.T3.IR(7))L:<br>IEN <-- 1, SC<.. 0<br>IOF<br>F040<br>(D7.I.T3.IR(6)L:<br>IEN <.. 0, SC<.. 0<br>Register reference instructions<br>Instruction<br>Memory reference instructions<br>Hexdecimal Boolean condition<br>Instruction Hexadecimal<br>Boolean condition<br>RTL<br>RTL<br>CLA<br>7800<br>D7.1.T3.IR(11))L:<br>AC <-- (0000), SC <-- 0<br>AND<br>(0, 8)ххх<br>DO.T4)L:<br>DR <-- M[AR]<br>CLE<br>7400<br>(D7.1.T3.IR(10))L:<br>E <-- (0), SC <.-0<br>DO.TS)L:<br>AC <-- (AC.DR)L, SC <-- 0<br>CMA<br>7200<br>(D7.1.T3.IR(9))L:<br>AC <-- AC', SC <-- 0<br>ADD<br>(1,9)ххх<br>DI.T4)L:<br>DR <-- M[AR]<br>СМЕ<br>7100<br>(D7.1'.T3.IR(8))L<br>E <--<br>E',SC <--0<br>DI.T5)L:<br>AC <--(AC+DR), SC <-- 0<br>CIR<br>7080<br>(D7.1.T3.IR(7))L:<br>AC(14:0) <.. AC(15:1),<br>AC(15) <-- E,E <-- AC(0). SC <--<br>LDA<br>(2, A)xxx<br>D2.T4)L:<br>DR <-- M[AR]<br>CIL<br>7040<br>(D7.1.T3.IR(6))L:<br>AC(15:1) <-- AC(14:0),<br>D2.T5)L:<br>AC <-- DR, SC <-- 0<br>AC(0) <.- E, E <.- AC(15), SC <. 0<br>INC<br>7020<br>(D7.1.T3.IR(5))L:<br>AC <-- AC+1, SC <-- 0<br>STA<br>(3. В)ххх<br>D3.T4)L:<br>M[AR] <-- AC, SC <-- 0<br>SPA<br>7010<br>(D7.1.T3.IR(4)L: (AC(15)](https://s3.us-east-1.amazonaws.com/storage.unifolks.com/qimg-008/008_b1ex50-rzgcgz20.jpeg)
Extracted text: column width=15 Appendix A Fetch and decode column width=26 column=10 column width=15 column width=26 Instruction Boolean condition RTL name Fetch TO)L: AR<--pc,><-- 0="" ti)l:=""><--><--pc+1 (do:d7)=""><--ir(12:14),><-- ir(15),="" row="" decode="" t2)l:=""><-- ir(0:11)="" hight-30="" indirect="" d7'.lt3)l:=""><--m[ar] input/output="" instructions="" instruction="" hexadecimal="" boolean="" condition="" rtl="" inp="" f800="" (d7.i.t3.ir(11))l:="" ac(0:7)=""><-. inpr,="" out="" f400="" (d7.i.t3.ir(10))l:="" out=""><-- ac(0:7),="" sc=""><-- 0="" ski="" f200="" (d7.i.t3.ir(9))l:="" (fgi)l:pc=""><-- pc+1,sc=""><-- 0="" sko="" f100="" (d7.1.t3.ir(8))l:="" (fgo)l:pc=""><- pc+1,sc=""><-- 0="" ion="" fo80="" (d7.1.t3.ir(7))l:="" ien=""><-- 1,=""><.. 0="" iof="" f040="" (d7.i.t3.ir(6)l:="" ien=""><.. 0,=""><.. 0="" register="" reference="" instructions="" instruction="" memory="" reference="" instructions="" hexdecimal="" boolean="" condition="" instruction="" hexadecimal="" boolean="" condition="" rtl="" rtl="" cla="" 7800="" d7.1.t3.ir(11))l:="" ac=""><-- (0000),="" sc=""><-- 0="" and="" (0,="" 8)ххх="" do.t4)l:="" dr=""><-- m[ar]="" cle="" 7400="" (d7.1.t3.ir(10))l:="" e=""><-- (0),="" sc=""><.-0 do.ts)l:="" ac=""><-- (ac.dr)l,="" sc=""><-- 0="" cma="" 7200="" (d7.1.t3.ir(9))l:="" ac=""><-- ac',="" sc=""><-- 0="" add="" (1,9)ххх="" di.t4)l:="" dr=""><-- m[ar]="" сме="" 7100="" (d7.1'.t3.ir(8))l="" e=""><-- e',sc=""><--0 di.t5)l:="" ac=""><--(ac+dr), sc=""><-- 0="" cir="" 7080="" (d7.1.t3.ir(7))l:="" ac(14:0)=""><.. ac(15:1),="" ac(15)=""><-- e,e=""><-- ac(0).="" sc=""><-- lda="" (2,="" a)xxx="" d2.t4)l:="" dr=""><-- m[ar]="" cil="" 7040="" (d7.1.t3.ir(6))l:="" ac(15:1)=""><-- ac(14:0),="" d2.t5)l:="" ac=""><-- dr,="" sc=""><-- 0="" ac(0)=""><.- e,="" e=""><.- ac(15),="" sc=""><. 0="" inc="" 7020="" (d7.1.t3.ir(5))l:="" ac=""><-- ac+1,="" sc=""><-- 0="" sta="" (3.="" в)ххх="" d3.t4)l:="" m[ar]=""><-- ac,="" sc=""><-- 0="" spa="" 7010="" (d7.1.t3.ir(4)l:="" (ac(15)")l:pc=""><-- pc+1,="" sc=""><.- bun="" (4,="" с)ххх="" d4.t4="" )l:="" pc=""><-- ar,="" sc=""><-- 0="" (d7.1'.t3.ir(3))l:="" (ac(15))l:pc=""><-- pc+1,="" sc=""><-- 0="" sna="" 7008="" sza="" 7004="" (d7.r.t3.ir(2))l::="" (ac="(0000))L:PC"><.. pc+1,="" sc=""><.- (="" bsa="" (5,="" d)xx="" ds.t4)l:="" m[ar]=""><-- pc,="" ar=""><-- ar+1="" ds.t5)l:="" pc=""><-- ar,="" sc=""><-- 0="" sze="" 7002="" (d7.1.t3.ir(1))l:="" (e="0)L:PC"><-- pc+1,="" sc=""><-- 0="" isz="" (6,="" e)xxx="" d6.t4)l:="" dr=""><.. m[ar]="" halt="" 7001="" (d7.i.t3.ir(0))l:="" s=""><-- 0,="" sc=""><-- 0="" d6.t5)l:="" dr=""><-- dr+1=""><-- dr,="" sc=""><-- 0,="" (dr=""><-- pc+1)="" row="" hight="30">
![The initial contents of the basic computer registers and memory are shown below. The table show the instruction fetching stage. You may use the tables in AppendixA.<br>Complete the highlighted cells in Table.1<br>Table.1 Basic computer register contents (all values are in hexadecimal<br>Control condition Register Transfer<br>D7 E<br>AC<br>DR<br>IR<br>PC<br>AR<br>M[AR]<br>000 195C,<br>000 195C,<br>000 195C,<br>294C,<br>200,<br>Initial Values<br>Initial Values<br>1041,<br>430,<br>1227<br>294C,<br>1041,<br>430,<br>31C,<br>8960,<br>TO:<br>AR<--- PC<br>294C,<br>1041,<br>430,<br>430,<br>7200,<br>T1:<br>IR<--- M[AR), PC <--- PC+1<br>T2:<br>AR<--- IR(0-11), I<---IR(15),D0:D7<---IR(14:12)<br>column width=16<br>column width=40<br>To set column width go the top row above rowl click the right mouse on column and set column width to see all the content of the column<br>](https://s3.us-east-1.amazonaws.com/storage.unifolks.com/qimg-008/008_5vex50-hapkop5i.jpeg)
Extracted text: The initial contents of the basic computer registers and memory are shown below. The table show the instruction fetching stage. You may use the tables in AppendixA. Complete the highlighted cells in Table.1 Table.1 Basic computer register contents (all values are in hexadecimal Control condition Register Transfer D7 E AC DR IR PC AR M[AR] 000 195C, 000 195C, 000 195C, 294C, 200, Initial Values Initial Values 1041, 430, 1227 294C, 1041, 430, 31C, 8960, TO: AR<--- pc="" 294c,="" 1041,="" 430,="" 430,="" 7200,="" t1:=""><--- m[ar),="" pc=""><--- pc+1="" t2:=""><--- ir(0-11),=""><><---ir(14:12) column="" width="16" column="" width="40" to="" set="" column="" width="" go="" the="" top="" row="" above="" rowl="" click="" the="" right="" mouse="" on="" column="" and="" set="" column="" width="" to="" see="" all="" the="" content="" of="" the="">