computer architecture, circuts
Circuit Lab 1 Circuit Lab 1 Given the following Boolean equations for outputs O1 and O2 _ _ _ O1 = ABC + ABC + B _ O2 = AB 1.) Draw the logic gate diagram for O1 and O2 using only three - 3 input AND gates and two - 2 input OR gates and two - inverters 2.) Create the truth table for O1 and O2 3.) Derive a minimized Boolean expression from the truth table using Kmaps Task A: Draw the circuit for a 4-bit seven-segment-display decoder: Step 1: Create a truth table for a four input (w,x,y,z) and seven-output (a,b,c,d,e,f,g) seven-segment display decoder. The outputs that are enabled for each input combination form the input number on the display. For example, the wxyz input combination of 0000 will enable outputs a,b,c,d,e,f but not g. This will form a zero on the seven segment display. The wxyz input of 10 through 15 should cause the display to show an “E” (stands for Error). Step 2: Derive the minimized Boolean expressions for outputs a through g using K-Maps Step 3: Draw the logic circuit for the seven-segment-display decoder using the minimized Boolean expressions Task B: Enable input Modify the design of your decoder by adding an enable bit (call it input k). If k is 1, the decoder should function normally. If k is zero, the seven segment should display zero regardless of the values on wxyz. 4 bit counter In this project you will create a 4 bit down counter that counts down from 9 to zero and then count 10. 11, 12 and then back to 9. You will design the logic of the circuit and also a chip level diagram. Your circuit will have a 4 bit output. It will be a finite state machine: Any input to your circuit other than zero through nine (0000 … 1001) ten, eleven and twelve(1010…1100), should reset the output to nine (1001). Your tasks are to document the following. Create a state transition diagram for your finite state machine based counter (do not forget transitions to state nine from unused states) 1. Specify the truth table (assuming D Flip Flops). 2. Derive necessary Boolean equations (using kmaps) 3. Draw gate-level logic diagram (logic gate symbols). _______________________________________________________________________________________________________ Chapter 11 Project Part II 2 bit integer division circuit In this project Design and implement a 2-bit integer division circuit. The circuit has four inputs A1, A0, B1, B0 and five outputs Q1, Q0, R1, R0, E. The values on A1, A0 and B1, B0 are treated as unsigned binary integer number A and B respectively: The circuit should generate the quotient Q and remainder R of the division A/B on lines Q1, Q0 and R1, R0 respectively. If division by zero is attempted, line E is set '1' (else E is '0') and the values on lines Q1, Q0, R1, R0 are considered invalid. Your tasks are to document the following. 1. Specify the truth table. 2. Derive necessary Boolean equations (using kmaps) 3. Draw gate-level logic diagram (logic gate symbols).