Change the MIPS processor design such that it executes one instruction per cycle. Extend the design of the MIPS processor with a hardware multiplier for binary numbers. Make it store the result of a...

Change the MIPS processor design such that it executes one instruction per cycle.

Extend the design of the MIPS processor with a hardware multiplier for binary numbers. Make it store the result of a multiplication in two 32-bit-wide registers H I and LO. The content of these registers is transferred to the general-purpose registers by instructions

a) Specify the exact semantics of the three new instructions.

b) What new components are present in the configurations of ISA and hardware?

c) Specify the effect of the new instructions.

d) Design the hardware extensions. Don’t forget clock enable signals for HI,L O and the write signal for g pr.