see attached
Building a 4-bit CPU Using the 4-bit ALU from Project 2 write a Verilog implementation of a simple 4-bit CPU. First you have to build (or use) the following modules: 1. 9-bit instruction register using nine D flip-flops (use D_flip_flop.vl). Include a clock pulse input that goes to all D flip-flops (see Fig 6.1 in the book, no need of clear input). Use gate level modeling. 2. Register file that includes four 4-bit registers (use the module provided in the template). 3. 4-bit ALU. This is the module you have implemented in Project 2 (you can use the behavioral model ALU4-behavioral.vl, but only if your ALU is not working properly). 4. LI instruction decoder. This is a module implementing a combinational circuit which outputs 0 when the LI opcode (100) is present at its inputs, and 1 otherwise. Use gate level modeling. 5. Quadruple 2x1 multiplexer (multiplexing 4-bit data) for the write data input of the register file. Use gate level modeling. See Fig. 4.26 in the book. Build the CPU as discussed in class Designing a CPU. Use the template provided in CPU_Template.vl. Read carefully the comment and add code as suggested. Testing. Create a test module that simulates running the following program on the CPU by loading the instruction register with the corresponding binary values for each instruction. Monitor the result of the execution of each instruction on the write data input of the register file. LI $2, 15 # load decimal 15 (unsigned binary) into $2 LI $3, 8 # load decimal 8 (unsigned binary) into $3 AND $1, $2, $3 # $1 = $2 AND $3 (two's complement -8) SUB $3, $1, $2 # $3 = $1 - $2 = -8 - (-1) = -7 SLT $2, $3, $0 # $2 = 1 ($3 < 0) add $1, $2, $3 # $1 = $2 + $3 = 1 + (-7) = -6 sub $1, $0, $1 # $1 = $0 - $1 = 0 - (-6) = 6 or $3, $1, $2 # $3 = $1 or $2 = 7 documentation. write a project report containing a description of the cpu (instruction set and logic diagrams), verilog source code for all modules and test results. show the test results by including the output from running the verilog test module. include also the translation of the test program into machine code (in binary). submission: submit the report file (ms word, pdf or html format) as an attachment to this assignment. project 2 answer 1: this is a 1-bit alu for bits 0 to 2 which can perform add, sub, and and or operations. verilog log code: `timescale 1ns / 1ps module alu_1bit(a,b,c,aluop,cout,aluout); input a,b,c; input [1:0] aluop; output cout,aluout; wire sum,aandb,aorb,b_in ; xor x1(b_in,b,aluop[0]); full_adder fa(.a(a),.b(b_in),.c(aluop[0]),.carry(cout),.s(sum)); and u1 (aandb,a,b); or u2 (aorb,a,b); mux_4to1_1bit u3(.in0(sum), .in1(sum), .in2(aandb), .in3(aorb), .sel(aluop), .out(aluout)); endmodule module full_adder(a, b, c, carry, s); input a, b, c; output carry, s; wire x1,x2,x3; xor(s,a,b,c); and( x1,a,b); and( x2,b,c); and( x3,c,a); or (carry,x1,x2,x3); endmodule module mux_4to1_1bit(in0, in1, in2, in3, sel, out); input in0, in1, in2, in3; input [1:0] sel; output out; assign out = sel[1] ? (sel[0] ? in3 : in2) : (sel[0] ? in1 : in0); endmodule answer 2: this is a 1-bit alu for the most significant bit. it includes a direct input that is connected to perform the set on less than operation and also has a direct output from the adder for the less than comparison. verilog log code: `timescale 1ns / 1ps module alu_msb3(a,b,aluop,cout,aluout); input [3:0] a,b; input [1:0] aluop; output cout,aluout; wire sum,aandb,aorb,b_in ; xor x1(b_in,b[3],aluop[0]); full_adder fa(.a(a[3]),.b(b_in),.c(aluop[0]),.carry(cout),.s(sum)); and u1 (aandb,a[3],b[3]); or u2 (aorb,a[3],b[3]); mux_4to1_1bit u3(.in0(sum), .in1(sum), .in2(aandb), .in3(aorb), .sel(aluop), .out(aluout)); endmodule module full_adder(a, b, c, carry, s); input a, b, c; output carry, s; wire x1,x2,x3; xor(s,a,b,c); and( x1,a,b); and( x2,b,c); and( x3,c,a); or (carry,x1,x2,x3); endmodule module mux_4to1_1bit(in0, in1, in2, in3, sel, out); input in0, in1, in2, in3; input [1:0] sel; output out; assign out = sel[1] ? (sel[0] ? in3 : in2) : (sel[0] ? in1 : in0); endmodule answer 3: this is a 4-bit alu which performs all the functions of the 1 bit alu. the inputs and outputs are also 4 bits. verilog log code: `timescale 1ns / 1ps module alu_4(a,b,aluop,carryout,z,overflow); input [3:0] a; input [3:0] b; input [1:0] aluop; output [3:0] z; output carryout; output overflow; wire cout0, cout1, cout2, cout3; alu_1bit bit0 (.a(a[0]), .b(b[0]), .c(aluop[0]), .aluop(aluop), .cout(cout0), .aluout(z[0])); alu_1bit bit1 (.a(a[1]), .b(b[1]), .c(cout0), .aluop(aluop), .cout(cout1), .aluout(z[1])); alu_1bit bit2 (.a(a[2]), .b(b[2]), .c(cout1), .aluop(aluop), .cout(cout2), .aluout(z[2])); alu_1bit bit3 (.a(a[3]), .b(b[3]), .c(cout2), .aluop(aluop), .cout(cout3),. aluout(z[3])); assign carryout = cout3; xor x1(overflow,cout2,cout3); endmodule module alu_1bit(a,b,c,aluop,cout,aluout); input a,b,c; input [1:0] aluop; output cout,aluout; wire sum,aandb,aorb,b_in ; xor x1(b_in,b,aluop[0]); full_adder fa(.a(a),.b(b_in),.c(c),.carry(cout),.s(sum)); and u1 (aandb,a,b); or u2 (aorb,a,b); mux_4to1_1bit u3(.in0(sum), .in1(sum), .in2(aandb), .in3(aorb), .sel(aluop), .out(aluout)); endmodule module full_adder(a, b, c, carry, s); input a, b, c; output carry, s; wire x1,x2,x3; xor(s,a,b,c); and( x1,a,b); and( x2,b,c); and( x3,c,a); or (carry,x1,x2,x3); endmodule module mux_4to1_1bit(in0, in1, in2, in3, sel, out); input in0, in1, in2, in3; input [1:0] sel; output out; assign out = sel[1] ? (sel[0] ? in3 : in2) : (sel[0] ? in1 : in0); endmodule answer 4: this is a test module for the 4-bit alu verilog log code: `timescale 1ns / 1ps module test_4bit; // inputs reg [3:0] a; reg [3:0] b; reg [1:0] aluop; // outputs wire carryout; wire [3:0] z; wire overflow; // instantiate the unit under test (uut) alu_4 uut ( .a(a), .b(b), .aluop(aluop), .carryout(carryout), .z(z), .overflow(overflow) ); initial begin // initialize inputs a = 0;b = 0;aluop = 0; // arithmatic operations #100; a = 0;b = 0;aluop = 0; #100; a = 1;b = 1;aluop = 1; #100; a = 1;b = 2;aluop = 0; #100; a = 3;b = 1;aluop = 1; #100; a = 4;b = 2;aluop = 1; #100; a = 5;b = 2;aluop = 1; #100; a = 6;b = 1;aluop = 1; #100; a = 7;b = 3;aluop = 0; // logical operations #100; a = 0;b = 0;aluop = 2; #100; a = 1;b = 1;aluop = 3; #100; a = 1;b = 2;aluop = 3; #100; a = 3;b = 1;aluop = 3; #100; a = 4;b = 2;aluop = 2; #100; a = 5;b = 2;aluop = 2; #100; a = 6;b = 1;aluop = 3; #100; a = 7;b = 3;aluop = 2; end endmodule testing: module test_4bit; // inputs reg [3:0] a; reg [3:0] b; reg [1:0] aluop; // outputs wire carryout; wire [3:0] z; wire overflow; // instantiate the unit under test (uut) alu_4 uut ( .a(a), .b(b), .aluop(aluop), .carryout(carryout), .z(z), .overflow(overflow) ); initial begin // initialize inputs a = 0;b = 0;aluop = 0; // arithmatic operations #100; a = 0;b = 0;aluop = 0; $display(a,b,z); #100; a = 1;b = 1;aluop = 0; $display(a,b,z); #100; a = 1;b = 2;aluop = 0; $display(a,b,z); #100; a = 3;b = 1;aluop = 0; $display(a,b,z); #100; a = 4;b = 2;aluop = 0; $display(a,b,z); #100; a = 5;b = 2;aluop = 0; $display(a,b,z); #100; a = 6;b = 1;aluop = 0; $display(a,b,z); #100; a = 7;b = 3;aluop = 0; $display(a,b,z); #100; a = 0;b = 0;aluop = 1; $display(a,b,z); #100; a = 1;b = 1;aluop = 1; $display(a,b,z); #100; a = 1;b = 2;aluop = 1; $display(a,b,z); #100; a = 3;b = 1;aluop = 1; $display(a,b,z); #100; a = 4;b = 2;aluop = 1; $display(a,b,z); #100; a = 5;b = 2;aluop = 1; $display(a,b,z); #100; a = 6;b = 1;aluop = 1; $display(a,b,z); #100; a = 7;b = 3;aluop = 1; $display(a,b,z); // logical operations #100; a = 0;b = 0;aluop = 2; $display(a,b,z); #100; a = 1;b = 1;aluop = 2; $display(a,b,z); #100; a = 1;b = 2;aluop = 2; $display(a,b,z); #100; a = 3;b = 1;aluop = 2; $display(a,b,z); #100; a = 4;b = 2;aluop = 2; $display(a,b,z); #100; a = 5;b = 2;aluop = 2; $display(a,b,z); #100; a = 6;b = 1;aluop = 2; $display(a,b,z); #100; a = 7;b = 3;aluop = 2; $display(a,b,z); #100; a = 0;b = 0;aluop = 3; $display(a,b,z); #100; a = 1;b = 1;aluop = 3; $display(a,b,z); #100; a = 1;b = 2;aluop = 3; $display(a,b,z); #100; a = 3;b = 1;aluop = 3; $display(a,b,z); #100; a = 4;b = 2;aluop = 3; $display(a,b,z); #100; a = 5;b = 2;aluop = 3; $display(a,b,z); #100; a = 6;b = 1;aluop = 3; $display(a,b,z); #100; a = 7;b = 3;aluop = 3; $display(a,b,z); end endmodule verilog results: simulation results: 0)="" add="" $1,="" $2,="" $3 ="" #="" $1="$2" +="" $3="1" +="" (-7)="-6" sub="" $1,="" $0,="" $1 ="" #="" $1="$0" -="" $1="0" -="" (-6)="6" or ="" $3,="" $1,="" $2 ="" #="" $3="$1" or="" $2="7" documentation. write="" a project="" report containing="" a description="" of="" the="" cpu="" (instruction="" set and logic="" diagrams),="" verilog source="" code for="" all="" modules="" and test="" results. show="" the="" test="" results="" by="" including="" the output="" from="" running="" the="" verilog="" test="" module. include="" also="" the="" translation="" of="" the test="" program into machine="" code (in="" binary).="" submission: submit="" the="" report="" file="" (ms="" word,="" pdf="" or="" html="" format)="" as="" an="" attachment="" to="" this="" assignment.="" project="" 2="" answer="" 1:="" this="" is="" a="" 1-bit="" alu="" for="" bits="" 0="" to="" 2="" which="" can="" perform="" add,="" sub,="" and="" and="" or="" operations.="" verilog="" log="" code:="" `timescale="" 1ns="" 1ps="" module="" alu_1bit(a,b,c,aluop,cout,aluout);="" input="" a,b,c;="" input="" [1:0]="" aluop;="" output="" cout,aluout;="" wire="" sum,aandb,aorb,b_in="" ;="" xor="" x1(b_in,b,aluop[0]);="" full_adder="" fa(.a(a),.b(b_in),.c(aluop[0]),.carry(cout),.s(sum));="" and="" u1="" (aandb,a,b);="" or="" u2="" (aorb,a,b);="" mux_4to1_1bit="" u3(.in0(sum),="" .in1(sum),="" .in2(aandb),="" .in3(aorb),="" .sel(aluop),="" .out(aluout));="" endmodule="" module="" full_adder(a,="" b,="" c,="" carry,="" s);="" input="" a,="" b,="" c;="" output="" carry,="" s;="" wire="" x1,x2,x3;="" xor(s,a,b,c);="" and(="" x1,a,b);="" and(="" x2,b,c);="" and(="" x3,c,a);="" or="" (carry,x1,x2,x3);="" endmodule="" module="" mux_4to1_1bit(in0,="" in1,="" in2,="" in3,="" sel,="" out);="" input="" in0,="" in1,="" in2,="" in3;="" input="" [1:0]="" sel;="" output="" out;="" assign="" out="sel[1]" (sel[0]="" in3="" :="" in2)="" :="" (sel[0]="" in1="" :="" in0);="" endmodule="" answer="" 2:="" this="" is="" a="" 1-bit="" alu="" for="" the="" most="" significant="" bit.="" it="" includes="" a="" direct="" input="" that="" is="" connected="" to="" perform="" the="" set="" on="" less="" than="" operation="" and="" also="" has="" a="" direct="" output="" from="" the="" adder="" for="" the="" less="" than="" comparison.="" verilog="" log="" code:="" `timescale="" 1ns="" 1ps="" module="" alu_msb3(a,b,aluop,cout,aluout);="" input="" [3:0]="" a,b;="" input="" [1:0]="" aluop;="" output="" cout,aluout;="" wire="" sum,aandb,aorb,b_in="" ;="" xor="" x1(b_in,b[3],aluop[0]);="" full_adder="" fa(.a(a[3]),.b(b_in),.c(aluop[0]),.carry(cout),.s(sum));="" and="" u1="" (aandb,a[3],b[3]);="" or="" u2="" (aorb,a[3],b[3]);="" mux_4to1_1bit="" u3(.in0(sum),="" .in1(sum),="" .in2(aandb),="" .in3(aorb),="" .sel(aluop),="" .out(aluout));="" endmodule="" module="" full_adder(a,="" b,="" c,="" carry,="" s);="" input="" a,="" b,="" c;="" output="" carry,="" s;="" wire="" x1,x2,x3;="" xor(s,a,b,c);="" and(="" x1,a,b);="" and(="" x2,b,c);="" and(="" x3,c,a);="" or="" (carry,x1,x2,x3);="" endmodule="" module="" mux_4to1_1bit(in0,="" in1,="" in2,="" in3,="" sel,="" out);="" input="" in0,="" in1,="" in2,="" in3;="" input="" [1:0]="" sel;="" output="" out;="" assign="" out="sel[1]" (sel[0]="" in3="" :="" in2)="" :="" (sel[0]="" in1="" :="" in0);="" endmodule="" answer="" 3:="" this="" is="" a="" 4-bit="" alu="" which="" performs="" all="" the="" functions="" of="" the="" 1="" bit="" alu.="" the="" inputs="" and="" outputs="" are="" also="" 4="" bits.="" verilog="" log="" code:="" `timescale="" 1ns="" 1ps="" module="" alu_4(a,b,aluop,carryout,z,overflow);="" input="" [3:0]="" a;="" input="" [3:0]="" b;="" input="" [1:0]="" aluop;="" output="" [3:0]="" z;="" output="" carryout;="" output="" overflow;="" wire="" cout0,="" cout1,="" cout2,="" cout3;="" alu_1bit="" bit0="" (.a(a[0]),="" .b(b[0]),="" .c(aluop[0]),="" .aluop(aluop),="" .cout(cout0),="" .aluout(z[0]));="" alu_1bit="" bit1="" (.a(a[1]),="" .b(b[1]),="" .c(cout0),="" .aluop(aluop),="" .cout(cout1),="" .aluout(z[1]));="" alu_1bit="" bit2="" (.a(a[2]),="" .b(b[2]),="" .c(cout1),="" .aluop(aluop),="" .cout(cout2),="" .aluout(z[2]));="" alu_1bit="" bit3="" (.a(a[3]),="" .b(b[3]),="" .c(cout2),="" .aluop(aluop),="" .cout(cout3),.="" aluout(z[3]));="" assign="" carryout="cout3;" xor="" x1(overflow,cout2,cout3);="" endmodule="" module="" alu_1bit(a,b,c,aluop,cout,aluout);="" input="" a,b,c;="" input="" [1:0]="" aluop;="" output="" cout,aluout;="" wire="" sum,aandb,aorb,b_in="" ;="" xor="" x1(b_in,b,aluop[0]);="" full_adder="" fa(.a(a),.b(b_in),.c(c),.carry(cout),.s(sum));="" and="" u1="" (aandb,a,b);="" or="" u2="" (aorb,a,b);="" mux_4to1_1bit="" u3(.in0(sum),="" .in1(sum),="" .in2(aandb),="" .in3(aorb),="" .sel(aluop),="" .out(aluout));="" endmodule="" module="" full_adder(a,="" b,="" c,="" carry,="" s);="" input="" a,="" b,="" c;="" output="" carry,="" s;="" wire="" x1,x2,x3;="" xor(s,a,b,c);="" and(="" x1,a,b);="" and(="" x2,b,c);="" and(="" x3,c,a);="" or="" (carry,x1,x2,x3);="" endmodule="" module="" mux_4to1_1bit(in0,="" in1,="" in2,="" in3,="" sel,="" out);="" input="" in0,="" in1,="" in2,="" in3;="" input="" [1:0]="" sel;="" output="" out;="" assign="" out="sel[1]" (sel[0]="" in3="" :="" in2)="" :="" (sel[0]="" in1="" :="" in0);="" endmodule="" answer="" 4:="" this="" is="" a="" test="" module="" for="" the="" 4-bit="" alu="" verilog="" log="" code:="" `timescale="" 1ns="" 1ps="" module="" test_4bit;="" inputs="" reg="" [3:0]="" a;="" reg="" [3:0]="" b;="" reg="" [1:0]="" aluop;="" outputs="" wire="" carryout;="" wire="" [3:0]="" z;="" wire="" overflow;="" instantiate="" the="" unit="" under="" test="" (uut)="" alu_4="" uut="" (="" .a(a),="" .b(b),="" .aluop(aluop),="" .carryout(carryout),="" .z(z),="" .overflow(overflow)="" );="" initial="" begin="" initialize="" inputs="" a="0;b" =="" 0;aluop="0;" arithmatic="" operations="" #100;="" a="0;b" =="" 0;aluop="0;" #100;="" a="1;b" =="" 1;aluop="1;" #100;="" a="1;b" =="" 2;aluop="0;" #100;="" a="3;b" =="" 1;aluop="1;" #100;="" a="4;b" =="" 2;aluop="1;" #100;="" a="5;b" =="" 2;aluop="1;" #100;="" a="6;b" =="" 1;aluop="1;" #100;="" a="7;b" =="" 3;aluop="0;" logical="" operations="" #100;="" a="0;b" =="" 0;aluop="2;" #100;="" a="1;b" =="" 1;aluop="3;" #100;="" a="1;b" =="" 2;aluop="3;" #100;="" a="3;b" =="" 1;aluop="3;" #100;="" a="4;b" =="" 2;aluop="2;" #100;="" a="5;b" =="" 2;aluop="2;" #100;="" a="6;b" =="" 1;aluop="3;" #100;="" a="7;b" =="" 3;aluop="2;" end="" endmodule="" testing:="" module="" test_4bit;="" inputs="" reg="" [3:0]="" a;="" reg="" [3:0]="" b;="" reg="" [1:0]="" aluop;="" outputs="" wire="" carryout;="" wire="" [3:0]="" z;="" wire="" overflow;="" instantiate="" the="" unit="" under="" test="" (uut)="" alu_4="" uut="" (="" .a(a),="" .b(b),="" .aluop(aluop),="" .carryout(carryout),="" .z(z),="" .overflow(overflow)="" );="" initial="" begin="" initialize="" inputs="" a="0;b" =="" 0;aluop="0;" arithmatic="" operations="" #100;="" a="0;b" =="" 0;aluop="0;" $display(a,b,z);="" #100;="" a="1;b" =="" 1;aluop="0;" $display(a,b,z);="" #100;="" a="1;b" =="" 2;aluop="0;" $display(a,b,z);="" #100;="" a="3;b" =="" 1;aluop="0;" $display(a,b,z);="" #100;="" a="4;b" =="" 2;aluop="0;" $display(a,b,z);="" #100;="" a="5;b" =="" 2;aluop="0;" $display(a,b,z);="" #100;="" a="6;b" =="" 1;aluop="0;" $display(a,b,z);="" #100;="" a="7;b" =="" 3;aluop="0;" $display(a,b,z);="" #100;="" a="0;b" =="" 0;aluop="1;" $display(a,b,z);="" #100;="" a="1;b" =="" 1;aluop="1;" $display(a,b,z);="" #100;="" a="1;b" =="" 2;aluop="1;" $display(a,b,z);="" #100;="" a="3;b" =="" 1;aluop="1;" $display(a,b,z);="" #100;="" a="4;b" =="" 2;aluop="1;" $display(a,b,z);="" #100;="" a="5;b" =="" 2;aluop="1;" $display(a,b,z);="" #100;="" a="6;b" =="" 1;aluop="1;" $display(a,b,z);="" #100;="" a="7;b" =="" 3;aluop="1;" $display(a,b,z);="" logical="" operations="" #100;="" a="0;b" =="" 0;aluop="2;" $display(a,b,z);="" #100;="" a="1;b" =="" 1;aluop="2;" $display(a,b,z);="" #100;="" a="1;b" =="" 2;aluop="2;" $display(a,b,z);="" #100;="" a="3;b" =="" 1;aluop="2;" $display(a,b,z);="" #100;="" a="4;b" =="" 2;aluop="2;" $display(a,b,z);="" #100;="" a="5;b" =="" 2;aluop="2;" $display(a,b,z);="" #100;="" a="6;b" =="" 1;aluop="2;" $display(a,b,z);="" #100;="" a="7;b" =="" 3;aluop="2;" $display(a,b,z);="" #100;="" a="0;b" =="" 0;aluop="3;" $display(a,b,z);="" #100;="" a="1;b" =="" 1;aluop="3;" $display(a,b,z);="" #100;="" a="1;b" =="" 2;aluop="3;" $display(a,b,z);="" #100;="" a="3;b" =="" 1;aluop="3;" $display(a,b,z);="" #100;="" a="4;b" =="" 2;aluop="3;" $display(a,b,z);="" #100;="" a="5;b" =="" 2;aluop="3;" $display(a,b,z);="" #100;="" a="6;b" =="" 1;aluop="3;" $display(a,b,z);="" #100;="" a="7;b" =="" 3;aluop="3;" $display(a,b,z);="" end="" endmodule="" verilog="" results:="" simulation="">