Because cache misses lead to pipeline stall, they increase the CPI of a pipelined processor. True False

Please solve given two questions in given figures please.

Extracted text: Because cache misses lead to pipeline stall, they increase the CPI of a pipelined processor. True False


Extracted text: Answer this question based on a direct-mapped cache design with the following bits (32-bit) of the address are used to access the cache. Tag: 31-10 Index: 9-5 Offset: 4-0 What is the cache block size (in words)? 12 4 8. We can't say by the given information.