Based on the steps performed by the hardware in response to an interrupt, estimate the delay (in terms of clock cycles) from the occurrence of an interrupt to the execution of the first instruction...

Based on the steps performed by the hardware in response to an

interrupt, estimate the delay (in terms of clock cycles) from the occurrence of an

interrupt to the execution of the first instruction inside the corresponding ISR. It

can be assumed that no other interrupt (of higher priority) has occurred during this

time.