1) The adder–subtractor circuit of Fig. 4.13 has the following values for mode input M and data inputs A and B. M A B(a) 0 0111 0110(b) 0 1000 1001(c) 1 1100 1000(d) 1 0101 1010(e) 1 0000 0001In each...

1) The adder–subtractor circuit of Fig. 4.13 has the following values for mode input M and data inputs A and B.
     M   A       B
(a) 0 0111 0110
(b) 0 1000 1001
(c) 1 1100 1000
(d) 1 0101 1010
(e) 1 0000 0001
In each case, determine the values of the four SUM outputs, the carry C, and overflow V.

Extracted text: B3 A3 B2 A2 BỊ A1 Во Ao M C4 C3 C2 Co FA FA FA FA S3 S2 So FIGURE 4.13 Four-bit adder-subtractor (with overflow detection)