Assuming logic signals have infinitely fast fall and rise times but are delayed by through a logic gate, draw the output waveforms of the two phase clock generators shown in Fig. 14.3(b). Assume the...

Assuming logic signals have infinitely fast fall and rise times but are delayed by through a logic gate, draw the output waveforms of the two phase clock generators shown in Fig. 14.3(b). Assume the delay blocks add delays of each and a clock frequency of 10 MHz is applied to the input.