Assume we are writing a testbench for a sequential circuit that has three control inputs (cA, cB, cC) and a periodic clock (clk). If we define CLK_PERIOD as a localparameter with a value of 50 (nsec),...

Assume we are writing a testbench for a sequential circuit that has three control inputs (cA, cB, cC) and a periodic clock (clk). If we define CLK_PERIOD as a localparameter with a value of 50 (nsec), write the testbench segment that would ensure all possible combinations of the control inputs were tested on a clock rising edge. This is can be done more elegantly if you define each time step in terms of the constant CLK_PERIOD. Your answer should include the statements that define clk, cA, cB, and cC over time. Hint: think of how you would show all combinations of three variables on a truth table and replicate that over time, where each combination is held over a timespan with a clock triggering edge.