Assume the following: • The memory is byte addressable. Part A • Memory accesses are to 1-byte words (not to 4-byte words). For this cache, list all of the hexadecimal memory addresses that will hit...

Computer Architecture Question, please do not copy your answers from chegg, they are wrong and I will down vote you.

Extracted text: Assume the following: • The memory is byte addressable. Part A • Memory accesses are to 1-byte words (not to 4-byte words). For this cache, list all of the hexadecimal memory addresses that will hit in set 3. • Addresses are 13 bits wide. Check all that apply. • The cache is two-way set associative (E = 2), with a 4-byte block size (B = 4) and eight sets (S = 8). V 0x062C The contents of the cache are as follows, with all numbers given in hexadecimal notation. V 0X062D V OX062E 2-way set associative cache V OX062F Line 0 Line 1 Set index Tag Valid Byte Byte Byte Byte Tag Valid Byte Byte Byte Byte 2 3 V 0x064C 1 2 3 V 0X064D 09 1. 86 30 3F 10 00 0 1 45 1 60 4F E0 23 38 1 00 BC OB 37 V 0X064E 2 EB 0 |- OB 0 V OX064F 3 06 0 |- 32 1 12 08 7B AD O 0x051C 4 C7 1 06 78 07 C5 05 1 40 67 C2 3B 5 6E 0 O OX051D 71 OB DE 18 4B - 6 91 1 A0 B7 26 2D FO 0 O OX051E - 46 0 DE 1 co 88 37 7 12 O OX051F The following figure shows the format of an address (1 bit per box). Indicate Submit Previous Answers Request Answer (by labeling the diagram) the fields that would be used to determine the following: CO. The cache block offset CI. The cache set index CT. The cache tag X Incorrect; Try Again; One attempt remaining