Assume a shared-memory multiprocessor with a number of processor/private cache units connected by a shared single-transaction bus. Our baseline cache coherence protocol is a MESI protocol, but we want...

Assume a shared-memory multiprocessor with a number of processor/private cache units connected by a shared single-transaction bus. Our baseline cache coherence protocol is a MESI protocol, but we want to investigate what performance gain can be achieved by using an update-based coherence protocol according to Section 5.4.4. We want to determine the time and traffic under the execution of a sequence of accesses with a MESI and with an update-based protocol by using the parameters in Consider the following sequence of accesses by the processors:

R1/X, R2/X, R3/X, R4/X, W1/X, R2/X, R3/X, W2/X, R1/X, R3/X.

(a) How many cycles does it take to execute the access sequence under the invalidationbased MESI protocol and under the update-based protocol, assuming the access costs for the protocol transactions to be as

(b) Compare the traffic generated by the invalidation-based MESI protocol and the update-based protocol using the data in and assuming that B is 32 bytes.