Assume a cache of 32 Kbytes organized as 4 K lines of 8 bytes each. The main memory is 64 MB organized logically as 8 M blocks of 8 bytes each. Determine how to split the address (s-r, r, w) for direct mapping. Determine how to split the address (s, w) for associative mapping. Determine how to split the address (s-d, d, w) for set associative mapping. Assume each cache set is 4 lines of cache.

Assume a cache of 32 Kbytes organized as 4 K lines of 8 bytes each. The main memory is 64 MB organized logically as 8 M blocks of 8 bytes each. Determine how to split the address (s-r, r, w) for...

Assume a cache of 32 Kbytes organized as 4 K lines of 8 bytes each. The main memory is 64 MB organized logically as 8 M blocks of 8 bytes each.
1. Determine how to split the address (s-r, r, w) for direct mapping.
2. Determine how to split the address (s, w) for associative mapping.
3. Determine how to split the address (s-d, d, w) for set associative mapping. Assume each cache set is 4 lines of cache.

Jun 02, 2022