As we know, with matched MOSFETs the VTC of a CMOS inverter is centered at the midpoint voltage vI 5 Vm 5 VDDy2. What if the devices are mismatched due to fabrication process variations? (a)...

As we know, with matched MOSFETs the VTC of a CMOS inverter is centered at the midpoint voltage vI 5 Vm 5 VDDy2. What if the devices are mismatched due to fabrication process variations? (a) Exploiting the fact that iDp 5 iDn, show for the case of devices not necessarily matched, the VTC is centered at

(b) Assuming VDD 5 5 V, fi nd the range of possible values for Vm if, for each FET, k may lie anywhere within the range of 100 A/V2 6 20%, and Vt may lie anywhere within the range of 1.0 V 6 20%. What is the maximum percentage range of variability of Vm from its ideal value of VDDy2 5 2.5 V? (c) What is the possible range of values for the peak current Im?