As we know, the emitter voltage of the CC confi guration follows the base voltage, but with an offset of about 0.7 V. This offset is often undesirable, as one would rather have the dc level of the output be the same as that of the input. The circuit of Fig. P2.725 uses a pnp CC stage, whose offset is 10.7 V, followed by an npn CC stage, whose offset is 20.7 V. The two offsets tend to cancel each other out, making the output dc level identical to that at the input. In particular, if the signal source has a zero dc component, so will the output. For this cancellation to be effective, we must have VBE2 5 VEB1. This can be achieved, for instance, if the BJTs have Is2 5 Is1 and we bias them identically by letting RE2 5 RE1. In the circuit shown, let the BJTs have F1 5 F2 5 100, VA1 5 VA2 5 `, and Is1 5 Is2.
(a) Assuming the signal source has a dc component of 0 V, fi nd the small-signal parameters Ri , Ro, and voyvi . Hint: to fi nd Ri , suitably adapt Eq. (2.58) and apply it twice; to fi nd Ro, suitably adapt Eq. (2.59) and apply it twice. (b) Assuming vsig 5 (5 V) cos t, fi nd all node voltages in the circuit, and express each one as the sum of its dc and ac component.