As we know, resistors are undesirable in MOS IC technology, so the circuit of Fig. P4.57 utilizes the pair M3-M4 in lieu of the resistance pair RD1-RD2. Let VDD 5 2VSS 5 2.5 V and RSS 5 100 kV, and...

As we know, resistors are undesirable in MOS IC technology, so the circuit of Fig. P4.57 utilizes the pair M3-M4 in lieu of the resistance pair RD1-RD2. Let VDD 5 2VSS 5 2.5 V and RSS 5 100 kV, and suppose ISS has been adjusted so that at dc balance each FET draws 100 A. Moreover, let Vt n 5 2Vt p 5 1.0 V, k9 n 5 2.5 k9 p 5 100 A/ V 2 , n 5 1y(10 V), p 5 1y(20 V), and n 5 0.2. (a) Specify the WnyLn ratio for the M1-M2 pair so as to achieve gmn 5 1.25 mA/V, and the WpyLp ratio for the M3-M4 pair so that at dc balance the circuit gives VO1 5 VO2 5 0 V. (b) Find vO(max) and vO(min), the upper and lower limits of the linear region of operation. (c) Find adm, acm, and the CMRR both for singleended and double-ended utilization. (d) How does a 610% mismatch in the p’s affect the CMRR for double-ended utilization? Hint: use acm 5 (vo1 2 vo2)yvic.