An SRAM latch with W=L D 0:2=0:1 transistor sizes for all transistors in 65-nm CMOS is designed. How much differential voltage is needed to reach a 6- probability that the latch toggles correctly...

An SRAM latch with W=L D 0:2=0:1 transistor sizes for all transistors in

65-nm CMOS is designed. How much differential voltage is needed to reach a 6-

probability that the latch toggles correctly from its meta-stable position.