An eight-bit CPU interacts with a two-way set-associative write-through cache organized in Little Endian format. The top row of this cache corresponds to set 0. The CPU address has the following...

An eight-bit CPU interacts with a two-way set-associative write-through cache organized in Little Endian format. The top row of this cache corresponds to set 0. The CPU address has the following format:

Data replacement policy in case of a miss is as follows:

(i) Tags with invalid bits are replaced.

(ii) The least significant tag is replaced if the number of references is the same when valid bit = 1 (every cache read or write is considered a reference).

(a) Draw the block diagram of the tag (with valid bits) and cache memories. Calculate how many bits are in each memory.

(b) Draw the block diagram and the contents of the cache and the tag memories at the end of the fifth, eleventh and thirteenth transactions according to the transaction list below: