An 8-bit single slope ADC with a 5 V reference uses a clock frequency of 1 M H z. Assuming that all of the other components are ideal, what is the limitation on the value of RC? What is the tolerance...

An 8-bit single slope ADC with a 5 V reference uses a clock frequency of 1 M H z. Assuming that all of the other components are ideal, what is the limitation on the value of RC? What is the tolerance of the clock frequency which will ensure less than 0.5 LSB of INL?

Discuss the advantages and disadvantages of using a dual-slope versus a single slope ADC architecture.