An 8 1 multiplexer has inputs A, B, and C connected to the selection inputs S2, S1, and S0, respectively. The data inputs I0 through I7 are as follows: (a) I1 = I7 = 0; I2 = I5 = I6 = 1; I0 = I4 = D;...

An 8

1 multiplexer has inputs A, B, and C connected to the selection inputs S₂, S₁, and S₀, respectively. The data inputs I0 through I7 are as follows:

(a) I₁
= I₇
= 0; I₂
= I₅
= I₆
= 1; I₀
= I₄
= D; and I₃
= D′.

(b) I₂
= I₃
= I₆
= 0; I₅
= 1; I₀
= I₁
= D; and I₄
= I₇
= D′

Determine the Boolean function that the multiplexer implements.

Write the HDL gate-level hierarchical description of a four-bit adder–subtractor for unsigned binary numbers. The circuit is similar to Fig. 4.13 but without output V. You can instantiate the four-bit full adder described in HDL Example 4.2. (HDL—see Problems 4.13 and 4.40)

Problems 4.13

The adder–subtractor circuit of Fig. 4.13 has the following values for mode input M and data inputs A and B.

M A B

(a) 0 0111 0110

(b) 0 1000 1001

(c) 1 1100 1000

(d) 1 0101 1010

(e) 1 0000 0001

In each case, determine the values of the four SUM outputs, the carry C, and overflow V.

(HDL—see Problems 4.37 and 4.40)