ALUDecoder.vhd
-- This is the code for ALUDecoder circuit--
-- Complete the code to achieve complete functionality--
-- Do NOT Change anything on ENTITY; Otherwise, it will not RUN with my TESTBENCH--
library IEEE;
use IEEE.std_logic_1164.all;
entity ALUDecoder is
port ( instruct: in std_logic_vector (31 downto 0);
ALUOp: in std_logic_vector (1 downto 0);
ALUControl: out std_logic_vector(2 downto 0));
end ALUDecoder;
architecture behavioral2 of ALUDecoder is
signal opcode, funct : std_logic_vector(5 downto 0); -- defining two signals
Opcode and funct, each 6 bit
-- These 2 signals are internal to this architecture
begin
funct
ALUControl
and funct= "100100") ) else
"001" when
-- COMPLETE THE REMAINING PART OF THE CODE BASED ON TABLE 2 --
--............................................................--
--............................................................--
--............................................................--
-- COMPLETE THE REMAINING PART OF THE CODE BASED ON TABLE 2 --
else "011"; -- This is the value if none of the conditions are
TRUE as ALU doesn't do anything if ALUControl= "011"
end behavioral2;
ControlUnit.vhd
-- This is the code for Full Control Unit circuit including MainDecoder and
ALUDecoder (Figure 2)--
-- Complete the code to achieve complete functionality--
-- Do NOT Change anything on ENTITY; Otherwise, it will not RUN with my TESTBENCH--
-- Use Main Decoder and ALUDecoder units as components and design ControlUnit using
structural Modeling
library IEEE;
use IEEE.std_logic_1164.all;
entity ControlUnit is
port ( instruct: in std_logic_vector (31 downto 0);
MemtoReg, MemWrite, Branch, ALUsrc, RegDst, RegWrite: out std_logic;
ALUOp: out std_logic_vector (1 downto 0);
ALUControl: out std_logic_vector(2 downto 0));
end ControlUnit;
architecture Structural of ControlUnit is
-- Include Components--
begin
-- Complete the Portmapping according to Fig. 2--
end Structural;
MainDecoder:
-- This is the code for MainDecoder circuit (Figure 2)--
-- Complete the code to achieve complete functionality--
-- Do NOT Change anything on ENTITY; Otherwise, it will not RUN with my TESTBENCH--
library IEEE;
use IEEE.std_logic_1164.all;
entity MainDecoder is
port ( instruct: in std_logic_vector (31 downto 0);
MemtoReg, MemWrite, Branch, ALUsrc, RegDst, RegWrite: out std_logic;
ALUOp: out std_logic_vector (1 downto 0));
end MainDecoder;
architecture behavioral1 of MainDecoder is
signal opcode, funct : std_logic_vector(5 downto 0); -- defining two signals
Opcode and funct, each 6 bit
begin
opcode
funct
RegWrite
else '0';
-- COMPLETE THE REMAINING PART OF THE CODE BASED ON TABLE 1 --
--............................................................--
--............................................................--
--............................................................--
-- COMPLETE THE REMAINING PART OF THE CODE BASED ON TABLE 1 --
-- You need to write the code to find the values of MemtoReg, MemWrite, Branch,
ALUsrc, RegDst,and ALUOp control signals;
-- RegWrite is already Provided
end behavioral1;
tb_ControlUnit.vhd
-- TESTBENCH FOR CONTROL UNIT:
-- FOR YOUR LAB 7: Test your designed control unit with this testbench
-- You do NOT need to write your own testbench
-- This testbench checks the control signals for 4 different instructions: lw, sw,
and (R Type), beq.
library IEEE;
use ieee.std_logic_1164.all;
ENTITY tb_ControlUnit IS
END tb_ControlUnit;
ARCHITECTURE tb_arch OF tb_ControlUnit IS
component ControlUnit is
port ( instruct: in std_logic_vector (31 downto 0);
MemtoReg, MemWrite, Branch, ALUsrc, RegDst, RegWrite: out std_logic;
ALUOp: out std_logic_vector (1 downto 0);
ALUControl: out std_logic_vector(2 downto 0));
end component;
--Inputs
signal instruct: std_logic_vector(31 downto 0);
--Outputs
signal MemtoReg, MemWrite, Branch, ALUsrc, RegDst, RegWrite: std_logic;
signal ALUOp: std_logic_vector (1 downto 0);
signal ALUControl: std_logic_vector (2 downto 0);
BEGIN
UUT: ControlUnit port map (
instruct =>instruct,
MemtoReg => MemtoReg,
MemWrite => MemWrite,
Branch => Branch,
ALUsrc => ALUsrc,
RegDst => RegDst,
RegWrite => RegWrite,
ALUOp=> ALUOp,
ALUControl => ALUControl);
Stimulus: process
begin
-- Checking control unit signals for load word instruction
--First instruction: 100011 10001 01000 0000000000000100 => [ lw $t0, 4 ($s1)]
instruct
wait for 10 ns;
-- Checking control unit signals for store word instruction
--second instruction: 101011 10001 10000 0000000000000000 => [ sw $s0, 0($s1)]
instruct
wait for 10 ns;
-- Checking control unit signals for R-Type (and) instruction
--third instruction: 000000 01001 01010 10000 00000 100000 => [ and $s0, $t1, $t2]
instruct
wait for 10 ns;
-- Checking control unit signals for beq instruction
--four instruction: 000100 10000 01001 0000000000000010 => [ beq $s0, $t1, 2]
instruct
wait for 10 ns;
wait;
end process;
END tb_arch;