A vending machine is an automated machine that provides items such as snacks and beverages to the consumers after the cash is inserted to the machine. For example, a vending machine to dispense...

A vending machine is an automated machine that provides items such as snacks and beverages
to the consumers after the cash is inserted to the machine. For example, a vending machine to
dispense candies where the vending machine accepts 10 cent and 20 cent coins only. The price
of the candy is 30 cents. Therefore, the machine will automatically dispense the candy
whenever it has received 30 cents. If it receives more that 30 cents, it will dispense the candy
with the balance money. In this assignment, you are required to propose and design a vending
machine controller for the above specifications. Assume that there are two outputs for the
vending machine controller, which are F and G. F = 1 and G = 0 indicate 30 cents have been
received and there is no balance money. F = 1 and G = 1 indicate the machine received more
that 30 cents and need to return the balance money.

Figure 1 show  the block diagram of FSM

the code down show Verilog program for the system

 you need to  do the tech bench  code  based on this Verilog program  and show the result in quertus.

module veding2(clk, rst, w, F, G, state);
   input clk, rst;
   input [1:0]w;
   output reg F, G;
   output reg [2:0] state;
    reg [2:0]next_state;
    parameter [2:0] zero=0, ten=1, twenty=2, thirty=3, fourty=4;
    // state register
    always@(posedge clk, posedge rst)
       if(rst) state <=>
        else state <=>
    //next_state and output logics
   always@(w, state)
        case(state)
            zero: begin F=0; G=0;
                      case(w)
                        2'b00: next_state = zero;
                             2'b01: next_state = ten;
                             2'b10: next_state = twenty;
                             default : next_state = zero;
                        endcase
                    end
            twenty: begin F=0; G=0;
                   case(w)
                        2'b00: next_state = ten;
                             2'b01: next_state = twenty;
                             2'b10: next_state = thirty;
                             default : next_state = ten;
                        endcase
                    end
            ten: begin F=0; G=0;
                   case(w)
                        2'b00: next_state = twenty;
                             2'b01: next_state = thirty;
                             2'b10: next_state = fourty;
                             default : next_state = twenty;
                        endcase
                    end
            thirty: begin F=1; G=0; next_state = zero; end
            fourty: begin F=1; G=1; next_state = zero; end
            default: begin F=0; G=0; next_state = zero; end
        endcase
endmodule