A synchronous Moore FSM has a single input, x_in, and a single output y_out. The machine is to monitor the input and remain in its reset state until a second sample of x_in is detected to be 1. Upon detecting the second assertion of x_in y_out is to assert and remain asserted until a fourth assertion of x_in is detected. When the fourth assertion of x_in is detected the machine is to return to its reset state and resume monitoring of x_in.1. (a) Draw the state diagram of the machine.2. (b) Write and verify an HDL model of the machine.
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