A synchronous finite state machine has an input xin and an output yout. When xin changes from 0 to 1, the output yout is to assert for three cycles, regardless of the value of xin, and then de-assert...

A synchronous finite state machine has an input xin and an output yout. When xin changes from 0 to 1, the output yout is to assert for three cycles, regardless of the value of xin, and then de-assert for two cycles before the machine will respond to another assertion of xin.

(a) Draw the state diagram of the machine.

(b) How many flip-flops are required for encoding all states? Assign each state with a unique binary code.

(c) Tabulate the state table of the machine.