A PLL is to operate with a reference clock frequency of 50 MHz and an output frequency of 2 GHz. Design a loop filter for the charge-pump phase comparator so that the loop bandwidth is approximately...

A PLL is to operate with a reference clock frequency of 50 MHz and an output frequency of 2 GHz. Design a loop filter for the charge-pump phase comparator so that the loop bandwidth is approximately 1/15th of the reference clock frequency and . Assume the VCO has and the charge-pump current is .