A PLL is to operate with a reference clock frequency of 10 MHz and an output frequency programmable over the range XXXXXXXXXXMHz by changing the divide ratio, . What value of results in the worst case...

A PLL is to operate with a reference clock frequency of 10 MHz and an output frequency programmable over the range 450 - 550 MHz by changing the divide ratio, . What value of results in the worst case loop bandwidth? Assuming , what range of voltages must be accommodated at ? Design the charge pump loop filter to have a loop bandwidth equal to 1/15th of the reference clock frequency and when the output frequency is set to 500 MHz and . Find the new values of when the output frequency is changed to 450 MHz and 550 MHz without changing the loop filter.