A microprocessor is clocked at a rate of 5 GHz. How long is a clock cycle? What is the duration of a particular type of machine instruction consisting of three clock cycles? A microprocessor provides...

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  1. A microprocessor is clocked at a rate of 5 GHz.



  1. How long is a clock cycle?



  1. What is the duration of a particular type of machine instruction consisting of three clock cycles?



  1. A microprocessor provides an instruction capable of moving a string of bytes from one area of memory to another. The fetching and initial decoding of the instruction takes 10 clock cycles. Thereafter, it takes 15 clock cycles to transfer each byte. The microprocessor is clocked at a rate of 10 GHz.



  1. Determine the length of the instruction cycle for the case of a string of 64 bytes.



  1. What is the worst-case delay for acknowledging an interrupt if the instruction is non-interruptible?



  1. What is the worse-case delay for acknowledging an interrupt if the instruction can be interrupted at the beginning of each byte transfer?





  1. Consider the timing diagram of Figure 12.10 in the 8th
    edition (or 14.10 in the 9th
    edition). Assume that there is only a two-stage pipeline (fetch, execute). Redraw the diagram to show how many time units are now required for four instructions.





  1. A pipelined processor has a clock rate of 2.5 GHz and executes a program with 1.5 million instructions. The pipeline has five stages and instructions are issued at a rate of one per clock cycle. Ignore penalties due to branch instruction and out-of-sequence executions.



  1. What is the speedup of this processor for this program compared to a non-pipelined processor, making the same assumptions used in Section 12.4 (or 14.4 in the 9th
    edition)?



  1. What is the throughput of the pipelined processor?





  1. a. What are some typical distinguishing characteristics of RISC organization?



b. Briefly explain the two basic approaches used to minimize register-memory operations on RISC machines.


  1. a. What is the essential characteristic of the superscalar approach to processor design?



b. What is the difference between the superscalar and superpipelined approaches?


  1. Do problem 14.2 a. in the 8th
    edition (or Problem 16.2 a in the 9th
    edition).



8. Do problem 14.2 b. in the 8th
edition (or Problem 16.2 b in the 9th
edition).
9. Do problem 14.2 c. in the 8th
edition (or Problem 16.2 c in the 9th
edition).
Answered Same DayDec 20, 2021

Answer To: A microprocessor is clocked at a rate of 5 GHz. How long is a clock cycle? What is the duration of a...

David answered on Dec 20 2021
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1. A microprocessor is clocked at a rate of 5 GHz.
a. How long is a clock cycle? 2 x 10-10
Length = 1/5GHz = 20 nsec
b. What is the duration of a particular type of machine instruction consisting
of three clock cycles?
Length = duration = 3* clock_length = 20 *3nsec = 60 nsec
6 x 10-10
2. A microprocessor provides an instruction capable of moving a string of bytes from one area of memory to another. The fetching and initial decoding of the instruction takes 10 clock cycles. Thereafter, it takes 15 clock cycles to transfer each byte. The microprocessor is clocked at a rate of 10 GHz.
a. Determine the length of the instruction cycle for the case of a string of 64 bytes.
Length of one clock cycle = 1/10GHz = 0.1 nsec
Length of instruction cycle = length of fetching and decoding + transfer of data
= [10 + 15*64] 0.1 ns
= 970 nsec
b. What is the worst-case delay for acknowledging an interrupt if the instruction is non-interruptible?
970 nsec
c. What is the worse-case delay for acknowledging an interrupt if the instruction can be interrupted at the beginning of each byte transfer?
In this case, the instruction can be interrupted after the instruction fetch, which takes 10 clock cycles, so the delay is 1 ns. The instruction can be interrupted between byte transfers, which results in a delay of no more than 15 clock cycles = 1.5 ns. Therefore, the worst-case delay is 1.5 ns.
3. Consider the timing diagram of Figure 12.10 in the 8th edition (or 14.10 in the 9th edition). Assume that there is only a two-stage pipeline (fetch, execute). Redraw the diagram to show how many time units are now required for four instructions.
    Instruction number
    Time
1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    Instruction
1
    FI
    DI
    
    
    
    
    
    
    
    
    Instruction
1
    
    CO
    FO
    
    
    
    
    
    
    
    Instruction
1
    
    
    EI
    WO
    
    
    
    
    
    
    Instruction
2
    
    
    
    FI
    DI
    
    
    
    
    
    Instruction
2
    
    
    
    
    CO
    FO
    
    
    
    
    Instruction
2
    
    
    
    
    
    EI
    WO
    
    
    
    Instruction
3
    
    
    
    
    
    
    FI
    DO
    
    
    Instruction
3
    
    
    
    
    
    
    
    CO
    FO
    
    Instruction
3
    
    
    
    
    
    
    
    
    EI
    WO
    Instruction number
    Time
11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    Instruction...
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