a/i4\J N IFdl O -v . -J cr1 q_a C\ (r dd\ \-_-io _b (sf ,*t l--,) l " 1+q-x l= \ -? IIIItIIlIIII 2. al. In Figure 81, what are the peak positive and negative values of Vou, for V;n equal to +10 V? (Hint: Use Thevenin's theorem.) (l) + 0.994,-0.994 (2) + 0.6,-7.519 (3) + 0.994,-7.519 (4) + 7.519-, 0.994 Y (orill Fig.81 -\ \ -. ,Y t r -In Fig. 81, if the diode (Dl) is reversedw, hat would be the peakp ositive and negative values of Vou, for Vin equal to +10 V peak? (1) + 0.994, -0.994 (2) + 0.6, -7.519 (Ilinr: Figs. 25 and 27) (3) + 0.994,-7.579 (4) + 7.519,-0.
a/ i4 \J N I F dl O - v . - J cr1 q_a C\ (r d d \ \_o--i _b (s- f ,*t l--,) l " 1+ q-x l= \ - ? I I I I t I I l I I I I 2. a l. In Figure 81, what are the peak positive and negative values of Vou, for V;n equal to +10 V? (Hint: Use Thevenin's theorem.) ( l ) + 0.994, - 0.994 (2) + 0.6, - 7.519 (3) + 0.994, -7.519 (4) + 7.519, - 0.994 Y (orill Fig.81 -\ \ - . , Y t r - In Fig. 81, if the diode (Dl) is reversed, what would be the peak positive and negative values of Vou, for Vin equal to +10 V peak? (1) + 0.994, - 0.994 (2) + 0.6, - 7.519 (Ilinr: Figs. 25 and 27) (3) + 0.994, -7.579 (4) + 7.519, -0.994 What is the cut-in angle for the circuit of Figure 82, forV6 = +10V peak? (L) 3.440" (2) 26.104 (3) 34.056' (4) 55.944" (Ifinn V,) -9!- 87 Fig.82 4. Zener diodes have a reverse.biased conduction-point voltage of (1) around 0.6 V (2) between 0.6 V and 5 V (3) greater thanZ V but less than 18 V (4) from 1.8 V to 200 V. 5. The circuit of Figure 83 uses two 5.I-V zener diodes. If Vin is a sine wave having peak value of +50 V, the output will be a (l) good square-wave approximation. (2) sawtooth wave form (3) a sine wave. v(rl + ! 0 Fig.83 6. In Figure 83, reducing the peak amplitude of V;n will tend to decrease the rise time of the output waveform. (l) True (2) False (Hint Exp.2) 7. Although LEDs are in fact diodes, and have characteristics other types of diodes, their principle application is as similar to (1) fast rectifiers (3) clipper diodes. (2) audio-frequency detectors. (4) display indicators. V (cal 88 I t I I I I I I I I I I I I I I I I i 8 . Figure 84 is a biased series cripper. If vb is greater than the peak varue ofV1n, Vou1, will be (Hint:Exp. 3) (l) equal to Vb (2) equal to (Vb + V,n) (3) zero. (4) equal to (Vb - V6) while Dl is conductine. v0.l o--{ Y! Fig.84 Fig.85 9' Figure 85 is a double-biased parailer clipper with a back-to_back zenerdiode shunt. what wil be the positive and negative peak output vortage?(All diodes have an inrernal banier potentiar or o.o v.) (r{inriNote gv)(l) +5.7, -5.7 (2) +8.6. _8.6 (3) +20, -20 @) +10.2. _tO.Z v(cd, will charge to 10. Figure 86 is an unbiased diode clamper. In this circuit, Cl a peak value through Dl, to (1) E, (+) at A withrespeCi to B. (z) (E - Vd), (-) at A with respecr to B. (3) (E + Vd), (+) at A with r.espect ro B, @) e, (-) at A with respect to B. v(h, \ l l'' 89 11 . 12. 13 . In Fig. 86 the maximum peak output voltage will be (HintExp.4) (1) E - Vd. (2) E + Vd. (3) 2E - Vd. (4) 2E In Fig. 86, the minimum peak output voltage will be (1) 0 v (2) + E. (3) - vd. (4) - E. Cl charges through Dl and discharges through Rl. In order to limit the magnitude of the discharge to a small fraction of the peak voltage across Cl, while permitting the circuit to respond to amplitude changes of Vin, the RC time constant should be (1) equal to the period of V;n. (2) twice the period of V;n. (3) between 5 and 10 times the period of V;n. (4) greater than 100 times the period of V;n. Figure 87 is a biased clamper circuit. The maximum peak output voltage is t4. Fig.87 15. The minimum peak output voltage is (1) -28 -Vb -Vd. (3) -E + 2Vb + Vd. (1) +Vb + Vd. (3) +2E + Vb + Vd. (2) +2E + Vd. (Hint: Fig. 86) (4) +Vb - Vd. V(o l l (2) -28 + Vb + Vd. (4) +E - Vb - Vd. when16. In the diode NAND gate of Figure 88, Y is in state (0) (1 )A=0 , B =1 , C= 1 . ( 2 )A= 1 ,B =1 , C= 1 . (3 )A=0 , B = 0 , C = 1 . ( 4 )A -0 , B =0 , C =0 . R g Y, (l2rl : I i I I I I I I t I I t I I I I I I 90 *o, o(t) f's : 0 iPu r l Fig.88 17. Figure 89 is a NOR gate. In this circuit, f = (l) when (1 ) A=0 ,B= l ,C=1 . ( 2 )A=1 ,B= l ,C=1 . (3 ) A=0 ,B=0 ,C= 1 . ( 4 )A=0 ,B=0 ,C=0 . 01 D5 R2 Fig.89 18. Figure 90 is an R-s flip-flop, built from 2 NoR gates. when s is in state (l) and R is in state (0), what is rhe srate of e and Q? ( l )Q= l ,Q=0 (2 )Q=0 ,Q=0 (3 )Q=0 ,Q=1 (4 )Q= l ,Q= l 9 1 Cv Fig.90 20. 21. (2) between 0 and l/2 A. (4) up to 10 mA. otn g(o : 19. Will the output change state if S is now brought to state (0)? (1) Yes (2) No In general, zener diode regulators, used as power supplies, selected for current requirements of (1) morethan 15A. (3) up to 1000 mA. An l8-V l-W zener diode should carry no more current than (1) I mA. (2) t8 mA. (3) 55 mA. are best (4) that required to regulate the loadyoltage.