Extracted text: A hidden passage is controlled by a redstone circuit for an adder which performs binary addition two bits at a time. He notes that it adds the inputs (x2i, y21) and (x2i+1, Y2i-1), the (2i)th and (2i+1)th bits of two binary numbers, and returns the sum as outputs s2i, S2+1. The addition is performed each clock cycle, starting from i = 0 until i = п 1, where n is the number of bits and 2 presumed to be even. For example, when adding x = 011010, and y number as x1:0 and y1:0 respectively. In this case, X1:0 is 10 and y1:0 = 01, and the carry bit co is 1. Our sum, s,0 is 00 and the next carry bit c, is 1. On the next clock cycle, we look at the next two 0110012, we take the first two bits of each bits, X3:2 = 10 and y3:2 = 10, so our sum s3-2 is 01, but we have a carry c4 1. Finally, our last addition to perform is on X5-4 = 01 and y5:4 = 01, with a carry bit c4 = 1. Our sum therefore is s54 = 11 with carry C6 = 0. Our final result of the addition is 1101002. You are only responsible for the addition of each two-bit partition of the number and carry bits, and are not responsible for the final sum or selecting two-bit partitions of the numbers. a) Fill in the state table for the new adder, the first row has been provided. X2i+1:2i Y2i+1:21 C2i C2i+2 S2i+1:2i X2i+1:2i Y2i+1:21 C2i C2i+2 S2i+1:2i 00 00 00
Extracted text: b) Draw a schematic design using a D flip-flop, two Full Adders, and a minimal network of AND, OR, and NOT gates. You only need to (do not be concerned how the next set of bits would be selected or passed into this circuit.) th scl natic the addition of given twe