(a) Describe the priority scheme and EOI scheme of 8259.
Refer Sections 14.3 and 14.4.
(b) Write down the format of ICW1 and ICW2 of 8259.
Refer Section 14.6.1.
(c) With respect to 8237, explain the DMA operation.
8237 is an advanced Programmable DMA controller. It provides a better performance compared
to 8257. This is capable of transferring a byte or a bulk of data between system memory and
peripherals in either direction. Memory to memory data transfer is also possible in this peripheral.
The 8237 can support four independent DMA channels which can be expanded to any number
after cascading more number of 8237.
8237 operates in two cycles such as passive cycle and active cycle. Each cycle contains a fixed
number of states. The 8237 can assume six states, when it is in active cycle. During idle cycle, it
is in idle state (SI).
The 8237 is initially in a state SI means an idle state where the 8237 does not have any valid
pending DMA request. During this time, although the 8237 may be idle, the CPU may program
it in this state. Once there is a DMA request, the 8237 enters state S0
, which is the first state of
the DMA operation. When the 8237 requests the CPU for a DMA operation and the CPU has
not acknowledged the request, the 8237 waits in S0
state. The acknowledge signal from the CPU
indicates that the data transfer may now begin. The S1
, S2
, S3
and S4
are the working states of DMA
operation, in which the actual data transfer is carried out. If more time is required to complete a
transfer than that is allowed, wait states may be inserted between S2
and S3
or S3
and S4
using the
READY pin of 8237. So it is clear that a memory read or a memory write DMA operation actually
requires four states S1
to S4
.