A CPU has a cache with block size 64 bytes. The main memory has k banks, each bank being cbytes wide. Consecutive c-byte chunks are mapped on consecutive banks with warp-around. All thek banks can be...

Downvote for incorrect

Extracted text: A CPU has a cache with block size 64 bytes. The main memory has k banks, each bank being cbytes wide. Consecutive c-byte chunks are mapped on consecutive banks with warp-around. All thek banks can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the k banks in parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes k/2 ns. The latency of one bank access is 80 ns. Ifc=2 and k=24, then latency of retrieving a cache block starting at address zero from main memory is