A CPU has 6 stages pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline followed by instruction decode, calculate effective address, fetch operands,...

Q2A CPU has 6 stages pipeline and runs at 1 GHz<br>frequency. Instruction fetch happens in the first<br>stage of the pipeline followed by instruction<br>decode, calculate effective address, fetch<br>operands, execute instruction and write back. A<br>conditional branch instruction computes the<br>target address and evaluates the condition in the<br>fourth stage of the pipeline. The processor stops<br>fetching new instructions following a condition<br>branch until the branch outcome is known. A<br>program executes 1010 instructions out of which<br>30% are conditional branch. If each instruction<br>takes 2 cycle to complete on average, then total<br>execution time of the program in seconds<br>

Extracted text: A CPU has 6 stages pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline followed by instruction decode, calculate effective address, fetch operands, execute instruction and write back. A conditional branch instruction computes the target address and evaluates the condition in the fourth stage of the pipeline. The processor stops fetching new instructions following a condition branch until the branch outcome is known. A program executes 1010 instructions out of which 30% are conditional branch. If each instruction takes 2 cycle to complete on average, then total execution time of the program in seconds

Jun 07, 2022
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