A CMOS inverter is implemented with matched FETs having k 5 200 A/V2 and Vt 5 0.6 V, and is powered from VDD 5 3 V. (a) Assuming 5 0, fi nd VIL, VIH, NML, NMH, Vm, and Im. (b) Find the output...

A CMOS inverter is implemented with matched FETs having k 5 200 A/V2 and Vt 5 0.6 V, and is powered from VDD 5 3 V. (a) Assuming 5 0, fi nd VIL, VIH, NML, NMH, Vm, and Im. (b) Find the output resistance for vO 5 VOL and for vO 5 VOH. (c) Find the maximum output current that the inverter can sink from and external load with its output within 0.1 V of ground, and can source to an external load with its output within 0.1 V of VDD. (d) Find the maximum output current that the inverter can source/sink while retaining noise margins of 1 V.