A bus master writes four bytes of data to the following address locations of a 32-bit wide byte-addressable memory (slave) organized in a Little Endian format: Following the write cycle, the same bus...

A bus master writes four bytes of data to the following address locations of a 32-bit wide byte-addressable memory (slave) organized in a Little Endian format:

Following the write cycle, the same bus master reads data (words) from the following slave addresses:

(a) Describe the contents of the memory after the writing and reading cycles shown above become complete.

(b) If the bus master generates the first address during the first clock cycle and keeps generating new addresses every time the slave responds with a Ready signal, what will be the values of the address, control and data entries in the timing diagram below? Assume that the bus master does not produce any Status signal comprised of Start, Cont, Busy and Idle.