A 5-stage pipelined processor has instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock...

Extracted text: A 5-stage pipelined processor has instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? I0: ADD $t2, $t1, $t2 Il: DIV $t4, $t3, $t2 12: MUL $t6, $t5, $t4 Answer: