A 32-bit RISC CPU organized in Big Endian format has three pipeline stages to execute the following two instructions: Draw the detailed ALU and the CPU schematic that executes these two instructions....

A 32-bit RISC CPU organized in Big Endian format has three pipeline stages to execute the following two instructions:

Draw the detailed ALU and the CPU schematic that executes these two instructions. Label all interconnections, bus widths and control signals.