4) We want to design a non-resetting sequence detector using a finite state machine with one input x and one output y. The FSM (Finite State Machine - State Diagram) asserts its output y when it...

Extracted text: 4) We want to design a non-resetting sequence detector using a finite state machine with one input x and one output y. The FSM (Finite State Machine - State Diagram) asserts its output y when it recognizes the following input bit sequence: "1011". The machine will keep checking for the proper bit sequence and does not reset to the initial state after it has recognized the string. [Note: As an example the input string X= "..1011011.." will cause the output to go high twice: Y = "..0001001.."] a) Draw the Mealy FSM (state diagram) b) Draw the Moore FSM (state diagram) (Only draw the state diagrams)