(4) Consider the following Edge Triggered D Type Flip-Flop with Set (S), Reset (R) and the D inputs. CK a b c defg hijk CK D Plot the Q output of this flip-flop considering the timing diagram above....

Extracted text: (4) Consider the following Edge Triggered D Type Flip-Flop with Set (S), Reset (R) and the D inputs. CK a b c defg hijk CK D Plot the Q output of this flip-flop considering the timing diagram above. 10


Extracted text: (3) Is the circuit below combinational logic or sequential logic? Explain in a simple fashion what the relationship is between the inputs and outputs. S- S- CLK- IRD