4. A computer has a 5-stage instruction pipeline of one cycle each. The 5 stages are: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Instruction Execution (IE), and Operand Store...

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Extracted text: 4. A computer has a 5-stage instruction pipeline of one cycle each. The 5 stages are: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Instruction Execution (IE), and Operand Store (OS). Consider the following code sequence, which is to be run on this computer. Label Action Code sequence STORE R16, Mem(12) Mem Address #12 € R16; LOAD R16, Mem(8) R16 E Mem(8); R7 E R16 – R4; SUB R7, R16, R4; BGT R7, NewAddr; SUB R5, R1, R4 AND R15, R5, R4 Branch to NewAddr if result is Greater than zero R5 E R4 - R1; R15 E R5 & R4; Do nothing NewAddr NOP (a) Suppose we modify the pipeline so that it has only one memory (that handles both instructions and data). In this case, there will be a structural (resource) hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data i.e. only ONE of instruction fetch, operand fetch and operand store can be operating in one cycle. Draw a pipeline diagram to show where the code above will stall. (b) In general, is it possible to reduce the number of stalls/NOPS resulting from this structural hazard by reordering the code? (c) Must this structural hazard be handled in hardware? We have seen that data hazards can be eliminated by adding NOPS to the code. Can you do the same with this structural hazard? If so, explain how. If not, explain why not. (d) Draw a pipeline diagram to show what happens if the BGT instruction is true. Assume that the next instruction to be executed when BGT instruction is true starts with instruction fetch after the instruction execution cycle of BGT instruction. (e) Show where is the occurrence of a data hazard in the above code. Draw a pipeline diagram to show how the hazard can be eliminated.